In semiconductor processing, integrated circuits are generally formed on dies on a wafer. Processing for forming the integrated circuits can be subject to variation and error. To address this, designers can implement test structures in the wafer, such as along scribe lines between dies. The test structures and/or the integrated circuit of each die can be subjected to testing to help ensure that each integrated circuit is fully functional.
Wafer level testing (or wafer sorting) is a testing mechanism for testing test structures and/or integrated circuits on a wafer prior to dicing (i.e., separating dice from the wafer). Wafer level testing uses probes to provide electrical signals to contact pads on the wafer, and can determine whether the integrated circuit or test structure under test is functional based on responses of the integrated circuit or test structure to the electrical signals. A probe head assembly having a probe card can provide an interface between the wafer to be tested and a processor-based controller that provides the electrical signals and receives the responses to those electrical signals as part of the wafer test routing.
Since batches of wafer being tested are often different, different probe cards may be needed to interface the test system with the current wafer under test. Changing probe cards is time consuming, and often the electric connections within the probe head assembly may become loose or damaged, causing further cost and delays.
Thus, there is a need for an improved probe head assembly.